{"id":"3e3e9f96-7977-4c28-a9e7-a4d4dcef9244","companyId":"59540430-33ee-404a-8921-39b23177cdec","modelName":"Biren BR100","slug":"biren-br100","description":"General-purpose GPU (GPGPU) for AI training and HPC. 77 billion transistors, 7nm TSMC dual-die chiplet design with CoWoS packaging. 256 TFLOPS FP32, 1024 TFLOPS BF16, 64GB HBM2E, 550W TDP. CUDA-compatible BIRENSUPA software stack. Single-die BR104 variant for PCIe cards. Manufacturing halted by TSMC after US Entity List designation in October 2023.","formFactor":"other","industryVertical":null,"environment":null,"maturityStage":"commercial","lifecycleState":"active","supersededByModelId":null,"specs":{},"manufacturerSerial":null,"reviewStatus":"reviewed","sources":[{"url":"https://www.hpcwire.com/2022/08/22/chinese-startup-biren-details-br100-gpu/","label":"Chinese Startup Biren Details BR100 GPU","title":"Chinese Startup Biren Details BR100 GPU","mediaType":"article","sourceName":"HPCwire"},{"url":"https://www.birentech.com/csr-article/gblwq16edn07xrb9pjky963s/","date":"2022-09-14","title":"Biren Technology company profile and BR100 series","sourceName":"Biren Technology"}],"aliases":[],"collisionRisk":"low","reviewNote":null,"manufacturerTermForTeleop":null,"keyFacts":[{"label":"BR100 series launch and stated use cases (company page)","value":"Biren Technology's company page says its BR100 series was released as a general-purpose GPU for cloud general computing, with stated target areas including AI training, inference, and graphics rendering. Treat those performance and market-positioning statements as company-stated (Biren Technology)."},{"label":"Biren general-computing focus (company page)","value":"The same company page describes Biren Technology as developing original general-computing systems and integrated hardware and software platforms, with cloud intelligent computing as an initial focus (Biren Technology)."},{"label":"BR100 die size transistors and FP32 peak","value":"HPCwire's Hot Chips 34 report on Biren's presentation lists the dual-die BR100 at 1,074 mm2 with 77 billion transistors on TSMC 7nm and 256 FP32 teraflops peak (HPCwire)."},{"label":"BR100 HBM TDP and die-to-die bandwidth","value":"The same Hot Chips coverage lists up to 64 GB HBM2E across four stacks, 550 W max TDP, 1 GHz target clock, and 896 GB/s die-to-die interconnect bandwidth (HPCwire)."}],"createdAt":"2026-08-25T13:04:55.374Z","updatedAt":"2026-10-09T21:59:08.556Z","unitsInFieldClaimed":null,"unitsInFieldVerified":null,"unitsManufacturedClaimed":null,"unitsManufacturedVerified":null,"unitsAsOf":null,"unitsSource":null,"salesModel":null,"priceUndisclosedSince":null,"autonomyClass":null,"autonomyStatement":null,"autonomyStatementSource":null,"demoForensics":null,"exportControlClass":null,"minCommitment":null,"warrantyTerms":null,"serviceModel":null,"productionRateClaimed":null,"productionRateEvidenced":null,"teleopRatioDisclosed":null,"interventionRateDisclosed":null,"jsonLd":{"@context":"https://schema.org","@type":"Product","@id":"https://registry.deploy.report/models/biren-br100","url":"https://registry.deploy.report/models/biren-br100","name":"Biren BR100","description":"General-purpose GPU (GPGPU) for AI training and HPC. 77 billion transistors, 7nm TSMC dual-die chiplet design with CoWoS packaging. 256 TFLOPS FP32, 1024 TFLOPS BF16, 64GB HBM2E, 550W TDP. CUDA-compatible BIRENSUPA software stack. Single-die BR104 variant for PCIe cards. Manufacturing halted by TSMC after US Entity List designation in October 2023.","identifier":"3e3e9f96-7977-4c28-a9e7-a4d4dcef9244","category":"other","publisher":{"@id":"https://deploy.report/#organization"}},"framework_metadata":{"framework_schema_version":"0.1.0","verification_status":"verified","maturity_stage":"commercial","lifecycle_state":"active","architectural_position":{"cohort":"other","sub_cohorts":[]},"within_cohort_verified_vs_claimed_pair":null,"cap_flags":[],"verification_depth":{"sources_count":2,"primary_source_types":[]}}}