AI chips

Ampere PCIe 150W inference GPU, 24 GB GDDR6. Successor to T4 in the mid-range inference tier.

Ampere-generation data-center GPU (SXM4 / PCIe), 40/80 GB HBM2e. The workhorse of AI training 2020-2023 and still dominant in the deployed base. TSMC 7nm.

China-specific export-compliant variant of the A100 Tensor Core GPU. Cut NVLink bandwidth to fit under the Oct 2022 BIS ceiling. Superseded Oct 2023 when BIS closed that workaround.

Blackwell-architecture data-center GPU, 700W TDP variant. Shipped alongside B200 for existing HGX chassis compatibility.

Full-power Blackwell data-center GPU (~1000W TDP), 192 GB HBM3e. The core building block of the GB200 superchip.

Automotive-safety-certified Blackwell-based SoC for L4 AV compute; adopted by Volvo, Polestar, XPENG, and others.

Two B200 GPUs + one Grace CPU on a single board via NVLink-C2C. Base unit of the GB200 NVL72 rack. The flagship 2024-2025 AI-training package.

Blackwell Ultra refresh of the Grace Blackwell superchip; announced GTC 2025 as the mid-cycle bump between Blackwell and the next Rubin architecture.

Hopper-architecture data-center AI GPU (SXM5 / PCIe). Dominant training + inference accelerator 2023-2024; 80 GB HBM3, ~700W TDP. Fabricated by TSMC on the 4N process.

Second-generation China-specific variant of Hopper. Introduced late 2023 after Oct 17 BIS rule blocked H800. Kept the memory (96 GB HBM3) and interconnect (900 GB/s NVLink) but sharply reduced dense compute (~148 FP16 TFLOPS vs H100's 989) to fit under BIS's performance-density threshold.

Hopper refresh with 141 GB HBM3e (from 80 GB); the mid-generation memory-bandwidth bump between H100 and Blackwell.

China-specific export-compliant variant of the H100 Tensor Core GPU. Cut the NVLink bandwidth (from 900 GB/s to 400 GB/s) to fit under the Oct 2022 BIS interconnect ceiling. Superseded Oct 2023 when BIS closed that workaround.

Ampere-based embedded AI compute module (32-64 GB), the dominant robotics-side Nvidia SKU 2022-2025 before Jetson Thor ramp.

Blackwell-based embedded AI compute module aimed at humanoid robots and autonomous machines; positioned as the successor to Jetson Orin.

Ada Lovelace data-center GPU (48 GB), targeted at mid-range training + inference + generative AI serving. Positioned between H100 and A10 in the Nvidia stack.

Turing-generation 70W PCIe inference GPU, 16 GB GDDR6. Dominant cloud inference SKU 2019-2022; still heavily deployed on AWS EC2 g4 + GCP T4 instances.

Volta-generation data-center GPU (2017), first with Tensor Cores. Legacy but still deployed in older DGX-1 and HPC clusters.

Seventh-generation TPU announced Cloud Next 2025; positioned as Google's first inference-first TPU generation.

Second-generation Cloud TPU (2017), first generation available on Google Cloud. Legacy.

Third-generation Cloud TPU (2018), first liquid-cooled generation. Still available on Google Cloud alongside newer generations.

Fourth-generation Tensor Processing Unit; optical-switch-networked pods, the foundation for PaLM / Gemini training through 2024. Fabricated by TSMC.

Cost-efficient TPU generation optimized for inference and smaller training runs; the mainstream Google Cloud TPU offering.

Performance-tier TPU v5 generation, aimed at large-model training; ~2x compute vs TPU v4.

Sixth-generation TPU announced May 2024; ~4.7x peak compute over TPU v5e. Backbone of Gemini 2.0-era training runs.

CDNA 2 PCIe accelerator (64 GB HBM2e), the mid-tier of the MI200 family. Broadly deployed in AMD-native HPC and inference clusters.

CDNA 2 data-center accelerator (128 GB HBM2e), pre-MI300 flagship. Powers Frontier + Aurora exascale HPC systems; still deployed in HPC + some AI training clusters.

CDNA 3 data-center accelerator with 192 GB HBM3, positioned as the primary alternative to Nvidia H100/H200 for LLM inference workloads. Fabricated by TSMC.

CDNA 3 refresh of MI300X with 256 GB HBM3e; announced late 2024. Bridge product before the MI350 series.

CDNA 4 next-generation accelerator (MI350X, MI355X) with 288 GB HBM3e and FP4/FP6 support. Announced 2024; ramping through 2025-2026.

Second-generation AWS custom inference accelerator; the Inf2 EC2 instance family. Sits alongside Trainium in AWS's LLM stack.

First-generation AWS custom training accelerator, launched 2022 in the Trn1 EC2 instance family. Fabricated by TSMC.

Second-generation Trainium announced re:Invent 2023; 4x training performance of Trn1. Backbone of the Anthropic Project Rainier deal.

Huawei's flagship domestic AI training accelerator, positioned as the primary Chinese alternative to Nvidia H100 after US export controls. Uses HBM3, Da Vinci architecture. Widely deployed at Chinese hyperscalers and government cloud regions.

Follow-on to 910B (2024), targeting ~60% of H100 training throughput on Da Vinci 3.0. Volume production ramping despite HBM supply constraints from Samsung/SK Hynix export restrictions.

Announced 2025 as the next generation targeting Nvidia B200 territory. Chiplet architecture per public disclosures; volume production timeline uncertain given SMIC 5nm-equivalent process constraints.

Second-generation Habana Gaudi AI training accelerator, positioned as Intel's Nvidia H100 alternative before Gaudi 3. Powers Intel Developer Cloud AI instances.

Third-generation Habana-designed AI accelerator, positioned as the mainline Intel alternative to Nvidia H100 for training + inference.

Meta Training and Inference Accelerator, first generation. Custom silicon for ranking + recommendation workloads before generative expansion.

Second-generation MTIA, ~3x compute per package, doubled memory bandwidth. Announced April 2024.

Qualcomm Robotics Platform SoC based on Snapdragon 865. Dominant chip in commercial drones (Skydio X10, others) and robotics. Integrated 15 TOPS NPU.

Qualcomm's automotive AV compute platform; unified ADAS + cockpit + digital-cluster SoC family for OEMs including GM, BMW, Stellantis. Fabricated by Samsung Foundry.

Next-generation Tenstorrent AI accelerator, positioned above Wormhole in the product stack. Announced 2024.

RISC-V-based AI accelerator with on-chip Ethernet mesh interconnect. Deployed in Tenstorrent's Galaxy servers.

Tesla's custom training accelerator for FSD neural nets; deployed in Dojo ExaPOD compute tiles at Tesla training clusters. Fabricated by TSMC.

Tesla's second-generation in-vehicle FSD compute board (2023-present); shipping in every new Model S/3/X/Y as the AV inference substrate. Believed fabricated by Samsung Foundry.

Alibaba T-Head Hanguang 800 inference NPU (2019). Powers Alibaba Cloud vision + recommendation inference across taobao/tmall. First-generation Chinese hyperscaler custom silicon at scale.

Baidu Kunlun 2 (7nm) AI accelerator, positioned for cloud training + inference. Powers Baidu ERNIE model serving. Kunlun 3 announced Oct 2024 as follow-on.

Shanghai-based Biren Technology's flagship GPGPU (2022 launch), positioned as domestic Chinese alternative to Nvidia A100. Development slowed post-US Entity List addition (2022) which cut TSMC access.

Cambricon's MLU370 series inference + training accelerator (7nm). Shanghai-listed Cambricon is a key domestic Chinese AI-chip player alongside Huawei and Biren.

Third-generation wafer-scale AI processor; 900,000 cores on a single ~46,000 mm² die. The largest chip made. Fabricated by TSMC.

First transformer-only ASIC; sacrifices generality for extreme throughput on transformer inference workloads. Announced June 2024.

Deterministic-compilation inference accelerator optimized for low-latency LLM token generation; SRAM-based memory architecture.

Sixth-generation Mobileye ADAS/AV SoC; family split between EyeQ6L (lite) and EyeQ6H (high-performance). Fabricated by STMicroelectronics with TSMC as second source (2025+).

Moore Threads (Chinese GPU startup founded by ex-Nvidia China exec) flagship data-center GPU. Positioned for both AI and graphics workloads. Founded 2020; on US Entity List 2023.

Reconfigurable Dataflow Unit optimized for enterprise LLM serving with large-parameter memory hierarchies.