AI chip · Google
Google TPU v6 (Trillium)
Sixth-generation TPU announced May 2024; ~4.7x peak compute over TPU v5e. Backbone of Gemini 2.0-era training runs.
On the DEPLOY graph: 1 campus carry a cited inventory line for it · 1 reference-design cluster include it.
Market position
Google's inference-optimised sixth generation (v6e). 4.7x TPU v5e per-chip FP16, 67% more memory bandwidth. Serves Gemini 1.5 Flash and Gemini 2 Nano-class workloads inside Google Cloud. v6p (Ironwood) is the training-optimised sibling.
DEPLOY editorial. What the vendor PDF cannot tell you.
Physical-AI cross-link
Derived from claims already on record (vendor first-party TDP, throughput, price, and the reference-design cluster registry). The arithmetic is shown per row so it can be audited. No estimated inputs.
- Perf per watt
- 9.18 FP8 TFLOPS/W1,836 TFLOPS ÷ 200 W = 9.18
- Cooling class (across reference designs)
- waterObserved across 1 reference-design cluster containing this chip
What fits in 32 GB
Weights-only footprint for public open-weight LLMs. Pure arithmetic: params × bytes/param. Excludes KV cache and activation memory; add ~10-30% headroom for real serving. A model that does not fit at FP16 may still fit at INT8 or INT4 with quality trade-offs. Not a benchmark.
| Model | Params | FP16 | INT8 | INT4 |
|---|---|---|---|---|
| Llama 3.1 8B dense | 8 B | 16 GB ✓ | 8 GB ✓ | 4 GB ✓ |
| Llama 3.1 70B dense | 70 B | 140 GB ✗ | 70 GB ✗ | 35 GB ✗ |
| Llama 3.1 405B dense | 405 B | 810 GB ✗ | 405 GB ✗ | 203 GB ✗ |
| Llama 3.3 70B dense | 70 B | 140 GB ✗ | 70 GB ✗ | 35 GB ✗ |
| DeepSeek V3 MoE (671B total, 37B active per token) | 671 B | 1342 GB ✗ | 671 GB ✗ | 336 GB ✗ |
| DeepSeek R1 MoE (671B total, 37B active per token) | 671 B | 1342 GB ✗ | 671 GB ✗ | 336 GB ✗ |
| Qwen 2.5 7B dense | 7 B | 14 GB ✓ | 7 GB ✓ | 4 GB ✓ |
| Qwen 2.5 72B dense | 72 B | 144 GB ✗ | 72 GB ✗ | 36 GB ✗ |
| Mixtral 8x7B MoE (46.7B total, 12.9B active per token) | 46.7 B | 93 GB ✗ | 47 GB ✗ | 23 GB ✓ |
| Mixtral 8x22B MoE (141B total, 39B active per token) | 141 B | 282 GB ✗ | 141 GB ✗ | 71 GB ✗ |
| Gemma 2 27B dense | 27 B | 54 GB ✗ | 27 GB ✓ | 14 GB ✓ |
| Command R+ dense | 104 B | 208 GB ✗ | 104 GB ✗ | 52 GB ✗ |
| Kimi K2 MoE (1T total, 32B active per token) | 1000 B | 2000 GB ✗ | 1000 GB ✗ | 500 GB ✗ |
Math: FP16 = params × 2 bytes; INT8 = params × 1 byte; INT4 = params × 0.5 bytes. MoE models sum every expert (full weights on disk), not the per-token active subset.
Common questions
Answer-first, sourced. Every claim below traces to a specific field on this page or a cited datasheet. FAQPage schema is emitted so LLM crawlers can lift these verbatim.
How much does Google TPU v6 (Trillium) cost?
Google TPU v6 (Trillium) launch pricing is not on record in the DEPLOY registry. Vendor list prices are typically published in the vendor's own briefing rather than the datasheet.
How much memory does Google TPU v6 (Trillium) have?
32 GB of HBM3 at 1,600 GB/s. Vendor datasheet, first-party.
How much power does one Google TPU v6 (Trillium) draw?
200 W TDP (thermal design power) per chip. System-level draw is higher: see the reference-design section for rack-level kW.
Which data centers have Google TPU v6 (Trillium)?
1 campus on the DEPLOY registry carry a cited inventory line for this chip. Full list below with per-campus quantity hints where published.
Which open-weight LLMs fit on one Google TPU v6 (Trillium)?
Of the 13 public open-weight LLMs DEPLOY tracks: 2 fit at FP16, 3 at INT8, 4 at INT4 (weights only, excludes KV cache). The full table is above with per-model math. Sparsity, offloading and multi-GPU serving change the picture; this row is single-chip weights-only.
Key facts
- Class
- Compute SoC (AI accelerator)
- Designer
- Safety-critical?
- No (data-center inference / training)
- Record as of
- 2026-08-25
- Latest cited claim
- 2024-05-01 (across 2 inventory + benchmark rows)
Specifications (9 fields, click to expand)
Vendor datasheet figures (first-party). Dense throughput first; sparse (2:4) in parentheses where NVIDIA quotes it. The exhaustive spec sheet lives on the datasheet URL below the table: this row set covers what buyers actually compare on.
- TDP
- 200 W
- Memory
- 32 GB HBM3
- Memory bandwidth
- 1,600 GB/s
- BF16 (dense)
- 918 TFLOPS
- FP8 (dense)
- 1,836 TFLOPS
- INT8 (dense)
- 1,836 TOPS
- Form factor
- OAM (Trillium pod, up to 256 chips)
- Announced
- 2024-05-14
- Released
- 2024-12-01
Source: vendor datasheet
Generation
Used in reference designs
The named rack-scale and pod-scale designs buyers actually order that contain this chip.
Compare with
Benchmarks
Published measurements per workload. Vendor datasheet numbers are first-party (verified posture); MLPerf / InferenceX / press results come in when their license terms + workload naming permit.
| Workload | Value | Unit | Source | As of |
|---|---|---|---|---|
| peak tflops bf16(~4.7x TPU v5e) | 918 | TFLOPS | vendor | 2024-05-01 |
Data centers stocking Google TPU v6 (Trillium)
Who has the most? →Every campus on the DEPLOY registry with a public claim of Google TPU v6 (Trillium) on site. Quantity hints are unstructured because underlying disclosures vary by order of magnitude.
- Google Fort Wayne / New Haven Data Centeras of 2024-05-01under constructioninferred
Google TPU capacity in Fort Wayne / New Haven campus (Trillium-generation)
Chip mix not published per-campus; inferred from Google's current-generation TPU deployment posture.
Sources
Adoption rows appear as we verify chip-integration claims per model. Every row is a public claim the maker or a tier-1 source has stated; verification tier (verified / reported / inferred) is shown per row. See every chip on record for the full catalog or the Google record.