Foundry · Company record
TSMC
AI chips fabricated at TSMC per public disclosures. As of 2026-08-25, 39 chips across 12 designers.
NVIDIA14 chips
- NVIDIA A10 Tensor Core GPU
Ampere PCIe 150W inference GPU, 24 GB GDDR6. Successor to T4 in the mid-range inference tier.
- NVIDIA A100 Tensor Core GPU
Ampere-generation data-center GPU (SXM4 / PCIe), 40/80 GB HBM2e. The workhorse of AI training 2020-2023 and still dominant in the deployed base. TSMC 7nm.
- NVIDIA B100 (Blackwell)
Blackwell-architecture data-center GPU, 700W TDP variant. Shipped alongside B200 for existing HGX chassis compatibility.
- NVIDIA B200 (Blackwell)
Full-power Blackwell data-center GPU (~1000W TDP), 192 GB HBM3e. The core building block of the GB200 superchip.
- NVIDIA DRIVE Thor
Automotive-safety-certified Blackwell-based SoC for L4 AV compute; adopted by Volvo, Polestar, XPENG, and others.
- NVIDIA GB200 Grace Blackwell Superchip
Two B200 GPUs + one Grace CPU on a single board via NVLink-C2C. Base unit of the GB200 NVL72 rack. The flagship 2024-2025 AI-training package.
- NVIDIA GB300 (Blackwell Ultra)
Blackwell Ultra refresh of the Grace Blackwell superchip; announced GTC 2025 as the mid-cycle bump between Blackwell and the next Rubin architecture.
- NVIDIA H100 Tensor Core GPU
Hopper-architecture data-center AI GPU (SXM5 / PCIe). Dominant training + inference accelerator 2023-2024; 80 GB HBM3, ~700W TDP. Fabricated by TSMC on the 4N process.
- NVIDIA H200 Tensor Core GPU
Hopper refresh with 141 GB HBM3e (from 80 GB); the mid-generation memory-bandwidth bump between H100 and Blackwell.
- NVIDIA Jetson AGX Orin
Ampere-based embedded AI compute module (32-64 GB), the dominant robotics-side Nvidia SKU 2022-2025 before Jetson Thor ramp.
- NVIDIA Jetson AGX Thor
Blackwell-based embedded AI compute module aimed at humanoid robots and autonomous machines; positioned as the successor to Jetson Orin.
- NVIDIA L40S
Ada Lovelace data-center GPU (48 GB), targeted at mid-range training + inference + generative AI serving. Positioned between H100 and A10 in the Nvidia stack.
- NVIDIA T4 Tensor Core GPU
Turing-generation 70W PCIe inference GPU, 16 GB GDDR6. Dominant cloud inference SKU 2019-2022; still heavily deployed on AWS EC2 g4 + GCP T4 instances.
- NVIDIA V100 Tensor Core GPU
Volta-generation data-center GPU (2017), first with Tensor Cores. Legacy but still deployed in older DGX-1 and HPC clusters.
Google7 chips
- Google TPU v7 (Ironwood)
Seventh-generation TPU announced Cloud Next 2025; positioned as Google's first inference-first TPU generation.
- Google TPU v2
Second-generation Cloud TPU (2017), first generation available on Google Cloud. Legacy.
- Google TPU v3
Third-generation Cloud TPU (2018), first liquid-cooled generation. Still available on Google Cloud alongside newer generations.
- Google TPU v4
Fourth-generation Tensor Processing Unit; optical-switch-networked pods, the foundation for PaLM / Gemini training through 2024. Fabricated by TSMC.
- Google TPU v5e
Cost-efficient TPU generation optimized for inference and smaller training runs; the mainstream Google Cloud TPU offering.
- Google TPU v5p
Performance-tier TPU v5 generation, aimed at large-model training; ~2x compute vs TPU v4.
- Google TPU v6 (Trillium)
Sixth-generation TPU announced May 2024; ~4.7x peak compute over TPU v5e. Backbone of Gemini 2.0-era training runs.
AMD5 chips
- AMD Instinct MI210
CDNA 2 PCIe accelerator (64 GB HBM2e), the mid-tier of the MI200 family. Broadly deployed in AMD-native HPC and inference clusters.
- AMD Instinct MI250X
CDNA 2 data-center accelerator (128 GB HBM2e), pre-MI300 flagship. Powers Frontier + Aurora exascale HPC systems; still deployed in HPC + some AI training clusters.
- AMD Instinct MI300X
CDNA 3 data-center accelerator with 192 GB HBM3, positioned as the primary alternative to Nvidia H100/H200 for LLM inference workloads. Fabricated by TSMC.
- AMD Instinct MI325X
CDNA 3 refresh of MI300X with 256 GB HBM3e; announced late 2024. Bridge product before the MI350 series.
- AMD Instinct MI350 series
CDNA 4 next-generation accelerator (MI350X, MI355X) with 288 GB HBM3e and FP4/FP6 support. Announced 2024; ramping through 2025-2026.
Amazon3 chips
- AWS Inferentia 2
Second-generation AWS custom inference accelerator; the Inf2 EC2 instance family. Sits alongside Trainium in AWS's LLM stack.
- AWS Trainium (Trn1)
First-generation AWS custom training accelerator, launched 2022 in the Trn1 EC2 instance family. Fabricated by TSMC.
- AWS Trainium 2
Second-generation Trainium announced re:Invent 2023; 4x training performance of Trn1. Backbone of the Anthropic Project Rainier deal.
Intel Corporation2 chips
- Intel Gaudi 2
Second-generation Habana Gaudi AI training accelerator, positioned as Intel's Nvidia H100 alternative before Gaudi 3. Powers Intel Developer Cloud AI instances.
- Intel Gaudi 3
Third-generation Habana-designed AI accelerator, positioned as the mainline Intel alternative to Nvidia H100 for training + inference.
Meta2 chips
- Meta MTIA v1
Meta Training and Inference Accelerator, first generation. Custom silicon for ranking + recommendation workloads before generative expansion.
- Meta MTIA v2
Second-generation MTIA, ~3x compute per package, doubled memory bandwidth. Announced April 2024.
Alibaba T-Head1 chip
- Alibaba Hanguang 800
Alibaba T-Head Hanguang 800 inference NPU (2019). Powers Alibaba Cloud vision + recommendation inference across taobao/tmall. First-generation Chinese hyperscaler custom silicon at scale.
Cerebras Systems1 chip
- Cerebras WSE-3 (Wafer-Scale Engine 3)
Third-generation wafer-scale AI processor; 900,000 cores on a single ~46,000 mm² die. The largest chip made. Fabricated by TSMC.
Other1 chip
- Etched Sohu
First transformer-only ASIC; sacrifices generality for extreme throughput on transformer inference workloads. Announced June 2024.
Qualcomm1 chip
- Qualcomm QRB5165
Qualcomm Robotics Platform SoC based on Snapdragon 865. Dominant chip in commercial drones (Skydio X10, others) and robotics. Integrated 15 TOPS NPU.
SambaNova Systems1 chip
- SambaNova SN40L
Reconfigurable Dataflow Unit optimized for enterprise LLM serving with large-parameter memory hierarchies.
Tesla1 chip
- Tesla Dojo D1
Tesla's custom training accelerator for FSD neural nets; deployed in Dojo ExaPOD compute tiles at Tesla training clusters. Fabricated by TSMC.
Rebuilt every 15 minutes. Chip → foundry map is hand-maintained in src/services/chips.ts. See every tracked foundry or every AI chip on record.