AI chip · SambaNova Systems
SambaNova SN40L
Reconfigurable Dataflow Unit optimized for enterprise LLM serving with large-parameter memory hierarchies.
Market position
SambaNova's Reconfigurable Dataflow Unit (RDU). 1.5 TB tier-3 memory per socket enables trillion-parameter models on 8 chips. Serves Samba-1 Composition of Experts. Used by SoftBank, Analog Devices, ArgonneNational Lab. Positioned against DGX H100 SuperPOD on memory-bound inference.
DEPLOY editorial. What the vendor PDF cannot tell you.
Physical-AI cross-link
Derived from claims already on record (vendor first-party TDP, throughput, price, and the reference-design cluster registry). The arithmetic is shown per row so it can be audited. No estimated inputs.
- Perf per watt
- 1.79 FP8 TFLOPS/W1,250 TFLOPS ÷ 700 W = 1.79
What fits in 1500 GB
Weights-only footprint for public open-weight LLMs. Pure arithmetic: params × bytes/param. Excludes KV cache and activation memory; add ~10-30% headroom for real serving. A model that does not fit at FP16 may still fit at INT8 or INT4 with quality trade-offs. Not a benchmark.
| Model | Params | FP16 | INT8 | INT4 |
|---|---|---|---|---|
| Llama 3.1 8B dense | 8 B | 16 GB ✓ | 8 GB ✓ | 4 GB ✓ |
| Llama 3.1 70B dense | 70 B | 140 GB ✓ | 70 GB ✓ | 35 GB ✓ |
| Llama 3.1 405B dense | 405 B | 810 GB ✓ | 405 GB ✓ | 203 GB ✓ |
| Llama 3.3 70B dense | 70 B | 140 GB ✓ | 70 GB ✓ | 35 GB ✓ |
| DeepSeek V3 MoE (671B total, 37B active per token) | 671 B | 1342 GB ✓ | 671 GB ✓ | 336 GB ✓ |
| DeepSeek R1 MoE (671B total, 37B active per token) | 671 B | 1342 GB ✓ | 671 GB ✓ | 336 GB ✓ |
| Qwen 2.5 7B dense | 7 B | 14 GB ✓ | 7 GB ✓ | 4 GB ✓ |
| Qwen 2.5 72B dense | 72 B | 144 GB ✓ | 72 GB ✓ | 36 GB ✓ |
| Mixtral 8x7B MoE (46.7B total, 12.9B active per token) | 46.7 B | 93 GB ✓ | 47 GB ✓ | 23 GB ✓ |
| Mixtral 8x22B MoE (141B total, 39B active per token) | 141 B | 282 GB ✓ | 141 GB ✓ | 71 GB ✓ |
| Gemma 2 27B dense | 27 B | 54 GB ✓ | 27 GB ✓ | 14 GB ✓ |
| Command R+ dense | 104 B | 208 GB ✓ | 104 GB ✓ | 52 GB ✓ |
| Kimi K2 MoE (1T total, 32B active per token) | 1000 B | 2000 GB ✗ | 1000 GB ✓ | 500 GB ✓ |
Math: FP16 = params × 2 bytes; INT8 = params × 1 byte; INT4 = params × 0.5 bytes. MoE models sum every expert (full weights on disk), not the per-token active subset.
Common questions
Answer-first, sourced. Every claim below traces to a specific field on this page or a cited datasheet. FAQPage schema is emitted so LLM crawlers can lift these verbatim.
How much does SambaNova SN40L cost?
SambaNova SN40L launch pricing is not on record in the DEPLOY registry. Vendor list prices are typically published in the vendor's own briefing rather than the datasheet.
How much memory does SambaNova SN40L have?
1500 GB of DDR5 (three-tier: 64 MB SRAM + 64 GB HBM3 + 1.5 TB DDR5). Vendor datasheet, first-party.
How much power does one SambaNova SN40L draw?
700 W TDP (thermal design power) per chip. System-level draw is higher: see the reference-design section for rack-level kW.
Which open-weight LLMs fit on one SambaNova SN40L?
Of the 13 public open-weight LLMs DEPLOY tracks: 12 fit at FP16, 13 at INT8, 13 at INT4 (weights only, excludes KV cache). The full table is above with per-model math. Sparsity, offloading and multi-GPU serving change the picture; this row is single-chip weights-only.
Key facts
- Class
- Compute SoC (AI accelerator)
- Designer
- SambaNova Systems
- Safety-critical?
- No (data-center inference / training)
- Record as of
- 2026-08-25
Specifications (8 fields, click to expand)
Vendor datasheet figures (first-party). Dense throughput first; sparse (2:4) in parentheses where NVIDIA quotes it. The exhaustive spec sheet lives on the datasheet URL below the table: this row set covers what buyers actually compare on.
- Process node
- TSMC N5
- TDP
- 700 W
- Memory
- 1500 GB DDR5 (three-tier: 64 MB SRAM + 64 GB HBM3 + 1.5 TB DDR5)
- FP16 (dense)
- 638 TFLOPS
- FP8 (dense)
- 1,250 TFLOPS
- Form factor
- PCIe (SN40L DataScale system)
- Announced
- 2023-09-19
- Released
- 2024-01-01
Source: vendor datasheet
Compare with
Sources
- SambaNova SN40L RDUSambaNova
Adoption rows appear as we verify chip-integration claims per model. Every row is a public claim the maker or a tier-1 source has stated; verification tier (verified / reported / inferred) is shown per row. See every chip on record for the full catalog or the SambaNova Systems record.